Engineering task
Embedded timing debug with the Rigol DS1054Z
Task: prove the timing relationship between reset, clock, firmware-controlled GPIO and a peripheral signal when an embedded board behaves intermittently.
Pick the signals that explain the fault
Use channel 1 on the power-good or reset line, channel 2 on a clock or timing reference, channel 3 on the firmware event and channel 4 on the peripheral response. This setup helps show whether the event order is correct.
Trigger on the event
Trigger on the signal that marks the problem: reset release, GPIO edge, PWM start or interrupt output. Adjust memory and timebase so you can see enough activity before and after the trigger. If the issue is rare, repeated captures can reveal whether the timing changes between good and bad cases.
What result should you get?
You should be able to answer a specific timing question: did reset release before the clock was stable, did the peripheral respond after the command, did the PWM begin before the enable line, or did a supply rail dip when the event occurred?
Why the DS1054Z fits
Four channels are often more useful than two when an embedded timing fault depends on the order of several signals.